1. Field of the Invention
The invention relates to implement a non-volatile memory on a semiconductor substrate, more particularly with an oxide-nitride-oxide layer structure.
2. Description of the Prior Art
Various nonvolatile memories have been disclosed in the prior art. Flash memory is one of the segments of nonvolatile memory devices. The device includes a floating gate to storage charges and an element for electrically placing charge on and removing the charges from the floating gate.
Normally, one of the applications of flash memory is BIOS for computer. Typically, the high-density nonvolatile memories can be applied as the mass storage of portable handy terminals, solid state camera and PC cards. That is because that the nonvolatile memories exhibit many advantages, such as a fast access time, low power dissipation, and robustness. It is proposed another cell array for portable computing and telecommunications application.
In the flash array schematic, field oxides (FOX) are formed between cells such that a polysilicon extension on FOX of each cell provides adequate gate coupling ratio. In the article, the access time is one of the key concerns for low voltage read operation.
As FIG. 1A, shows that the shallow trench isolation 121 all are separated each other and there are an estimated cell region 151 and an estimated periphery region 150. Then, the first-type ion region 122 such as doping p-type well is formed into the semiconductor substrate 120. Also, this second ion normally is boron, and the first photoresist 160 is used as an implanting mask by the conventional photolithography.
As FIG. 1B, the second-type ion region 123 such as doping n-type well is formed into semiconductor substrate 120. Also, this first ion normally is phosphorus, and the second photoresist 161 is used as an implanting mask by the conventional photolithography.
As FIG. 1C, a first oxide layer such as silicon oxide layer is grown on the surface of semiconductor substrate 120. Then, this first oxide layer is removed. Again, the second oxide layer 126 that is the tunnel oxide layer is grown on the semiconductor substrate 120. A first polysilicon layer 127 is blankly and conformably deposited over the surface of the second oxide layer 126.
As FIG. 1D, portions of the first polysilicon layer 127 and the portions of the second oxide layer 126 both located on the periphery region 150 are etched using the dry etching. Also, the portions of the first polysilicon layer 127 and the portions of the second oxide layer 126 both located on the cell region 150 are remained.
As FIG. 1E, the third oxide layer 128 is blankly formed on the first polysilicon layer 127 using the low-pressure chemical vapor deposition (LPCVD). Then, the first nitride layer 129 is deposited on the surface of the third oxide layer 128 the low-pressure chemical vapor deposition (LPCVD). Again, the fourth oxide layer 130 is deposited on the surface of the first nitride layer 129 the low-pressure chemical vapor deposition (LPCVD). Thus, a sandwich-type Oxide 128-Nitride 129-Oxide 130 layer can be formed. The photoresist 160 is formed on the top surface of the semiconductor as the implanting mask. Then, the first-type ion region 124 such as doping p-type well is formed into the semiconductor substrate 120. Also, this first ion normally is B, and the Oxide 128-Nitride 129-Oxide 130 dielectric layer is used as an implanting screen oxide by the conventional photolithography.
As FIG. 1F, the second-type ion region 125 such as doping n-type well is formed into semiconductor substrate 120. Also, this first ion normally is phosphrous or arsemic, and the Oxide 128-Nitride 129-Oxide 130 dielectric layer is used as an implanting screen oxide by the conventional photolithography.
As FIG. 1G, portions of the oxide 128-nitride 129-oxide 130 dielectric layer located on the periphery region 150 are etched using the conventional photolithography. Also, the other portions of the oxide 128-nitride 129-oxide 130 dielectric layer are still remained on the cell region 151.
As FIG. 1H, a fifth oxide layer 131 is grown over the periphery region 150 located on the surface of semiconductor substrate 120.
As FIG. 1I, the portions of the fifth oxide layer 131 located on the shallow trench isolation 121 of the periphery region 150, the fifth oxide layer 131 located on the second type ion region 125 and the first ion region 124 are all etched using the conventional dry etching. Thus, the other portions of the fifth oxide layer 131 located on the second type ion region 123 and the first ion region 122 are still remained.
As FIG. 1J, a sixth oxide layer 132 is grown over the surface of the semiconductor substrate 120, the second ion region 123 and the first ion region 122 using the furnace.
As FIG. 1K, a second polysilicon layer 133 is deposited on the surface of oxide layer 132 and the surface of the fourth oxide layer 130.
As FIG. 1L, the portions of the second polysilicon layer 133 is etched using the dry etching until the shallow trench isolation 121 is exposed. The other portions of the second polysilicon layer are still remained on the surface of the first-type ion region 122, the second-type ion region 123, the first-type ion region 124 and the second-type ion region 125 that are all located on the periphery region 151, and still remained on the surface of the oxide 128-nitride 129-oxide 130 dielectric layer that are located on the cell region 151. Thus, the capacitor column are formed.
According to the prior art, it can not be used as a higher voltage cell. Also, some of fabrication steps such as photo-mask step and furnace step are extra for the whole manufacture process. The loss of oxide are still high.
In accordance with the present invention, a method is provided for forming an implement non-volatile memory that substantially reduces the loss of oxide.
According to the preferred embodiment of this present invention, it can be used as a 3.3 voltage cell.
Also, some of fabrication steps such as photo-mask step and furnace step can be reduced for the whole manufacture process. The good quality for Sandwich-like type, such as Oxide-Nitride-Oxide layer can be obtained.
Therefore, in one embodiment, according to the above description, a plurality of trench isolation regions are formed in the semiconductor substrate. The isolation regions is separated from each other by an active region, wherein some of the active regions are located in a cell region of the semiconductor substrate, and the other of the active regions are located in a periphery region of the semiconductor substrate.
Then, firstly implanting ions of a first conductivity type into the active regions of the semiconductor substrate with a first voltage is carried out. Thus, a first ion region of the first conductivity type is formed, wherein the firstly implanting step is performed by using a first photoresist layer as mask. Next, the first photoresist removed. Again, firstly implanting ions of a second conductivity type into the active regions of the semiconductor substrate with a first voltage is carried out. Thus, a first ion region of the second conductivity type is formed, wherein the firstly implanting step is performed by using a second photoresist layer as mask, which is configures to make the first ion region of the second conductivity type be neighboring to the first ion region of the first conductivity type. Next, the second photoresist is removed.
Secondly implanting ions of the first conductivity type into the active regions of the semiconductor substrate with a second voltage is carried out. Thus, a second ion region of the first conductivity type is formed, wherein the secondly implanting step is performed by using a third photoresist layer as mask, which are configures to make the second ion region of the first conductivity type be neighboring to the first ion region of the second conductivity type. Then, the third photoresist is removed. Again, secondly implanting ions of the second conductivity type into the active regions of the semiconductor substrate with a second voltage is carried out. Thus, a second ion region of the second conductivity type is formed, wherein the secondly implanting step is performed by using a fourth photoresist layer as mask, which are configures to make the second ion region of the second conductivity type be neighboring to the second ion region of the first conductivity type. Then, the fourth photoresist is removed.
Then, a first oxide layer is deposited on the semiconductor substrate. The first oxide layer is removed. A second oxide layer is deposited on the semiconductor substrate. A portion of second oxide is removed, wherein fifth photoresist is used as an etching mask over first-type ion region on periphery region by first voltage implanting and the second-type region on periphery region by the first voltage implanting. Thus, a portion of second oxide layer is remained on and over the surface of first-type ion region and second-type ion region that are both formed by the first voltage implanting. The fifth photoresist is removed. A third oxide layer is formed on the second silicon dioxide layer and semiconductor substrate. A first polysilicon layer is blanket and conformably formed on the third oxide layer. A sixth photoresist is formed on first polysilicon layer to define an opening in the first polysilicon layer, wherein the opening is located between the periphery region and the cell region. The first polysilicon layer is etched until the trench isolation region is exposed, so that opening is formed and the sixth photoresist is used as an etching mask. The sixth photoresist is removed. A fourth oxide layer is formed over first polysilicon layer and the opening. Next, a first nitride layer is formed over the fourth oxide layer. Then, a fifth oxide layer is formed over the first nitride layer. A seventh photoresist is formed over the fifth oxide layer located on cell region to expose the periphery region.
Consequentially, the fourth oxide layer, the second nitride layer and the fifth oxide layer located on periphery region are all etched until the surface of the trench isolations located under the opening being exposed, wherein the seventh photoresist is used as an etching mask for leaving portions of the fourth oxide layer, the second nitride layer and the fifth oxide layer located on the periphery region. The second polysilicon on is formed the first polysilicon located on the periphery region and on the third oxide layer located on the cell region. A eighth photoresist is formed on the active region of the second conductive layer, wherein the active regions being on the first ion region of the first conductivity type and the first ion region of the second conductivity type.
A portion of the second polysilicon layer, a portion of the first polysilicon layer, a portion of the third oxide layer and a portion of the second oxide layer are all etched until the surface of trench isolation is exposed. Thus, capacitor columns are formed, some of the capacitor columns include the second polysilicon layer, the first polysilicon layer and the third oxide layer located on the periphery region. Some of the capacitor columns include the second polysilicon layer, the first polysilicon layer, the third oxide layer and the second oxide layer on the periphery region. The other of capacitor columns include the second polysilicon layer, the fourth oxide layer, the first nitride layer, the fifth oxide layer, the first polysilicon layer and the third oxide layer on the cell region.